In designing wiring patterns for semiconductor integrated circuits, signal delay times have been taken into consideration. For example, Japanese Patent Application Laid-open No. 4-245456 discloses controlling the number of traces intersecting a noted or intended trace so as to reduce variations in signal delay time. It is also known from Japanese Patent Application Laid-Open No. 6-83911 that in searching for a wiring route or channel, a forbidden region can be set so that parallel wiring lengths are restricted in the region, whereby a signal delay time developed by parallel traces is reduced.